In many semiconductor integrated circuit (IC) applications, it is desirable and necessary to pass information between different, physically separate portions of the IC. For example, within a microprocessor IC, address and data paths travel between the various functional blocks, such as adders, register banks and caches. Similarly, data travels between the various ports of a network switching device. In this latter case, it is common that there are multiple sets of data traveling between various portions of the device. For example, the chip may be transmitting data from a first input port to a first output port, while it is simultaneously transmitting data between a second input port and a second output port. Therefore, there is a need to quickly and efficiently allow the movement of data between a plurality of destinations within the IC. A variety of methods have been designed to address this issue. FIG. 1 shows a simple circuit where each input is directly wired to each output. At each output, there is a multiplexer, which selects one of the inputs to present to the output. In this case, each input has a connection to each output. Thus, if there are N inputs and N outputs, a total of N*N, or N2 connections, or wires, are needed. At small values of N, such as that shown in FIG. 1, this is acceptable. However, as the value of N increases, the number of wires increases exponentially, thereby becoming impractical. For example, if N is equal to three, there are only nine connections, as shown in FIG. 1. However, if N has a value of ten, one hundred connections are needed.
Large numbers of connections create complications within the IC, as there is only a limited amount of space within the IC that can be used for routing wires. In a typical semiconductor process, there are a number of layers, where some of these layers are used for the actual semiconductor devices, such as logic functions, memories, transistors and diodes, and the other layers are used to route the wires that connect these various devices together. Typically, there may be four layers within the semiconductor chip that are dedicated specifically to global routing. Also, space between functional blocks may be reserved for routing as well. This space is known as routing channels.
As the number of connections grows, the amount of space needed to route these wires grows as well. The routing layers are typically arranged such that one has all of its connections traveling in the X direction, while another has all of its connections traveling in the Y direction. Therefore, if a connection is not a straight line, it will have to use valuable space on multiple routing layers to achieve the required connection. Therefore, it is a goal of semiconductor design to keep the connections as short and as straight as possible to minimize the amount of routing space that is consumed.
To minimize the number of wires needed to connect a set of inputs to a set of outputs, a cross bar switch can be used. As shown in FIG. 2, each input is connected to a single wire, which crosses a wire associated with each output. To connect the specific input to a specific output, the switch lying at the intersection of the two wires is closed, thereby connecting the two. As can be seen in FIG. 2, the cross bar switch can significantly reduce the number of connections or wires within an IC. In this implementation, where there are N inputs and N outputs, a total of 2*N wires is needed. Thus, a cross bar switch uses N/2 times fewer wires than the directly wired circuit of FIG. 1. In the case where N is equal to three, a total of six wires are needed. In the case where N is equal to ten, a total of only twenty wires is needed, which is one fifth of the number needed by the circuit of FIG. 1. In situations where busses of 32 or 64 bits are employed, the savings are even more considerable. This represents a significant improvement over the embodiment of FIG. 1, and is therefore used in many implementations.
A second complication in the routing of wires within a IC device is timing. Each wire within an IC has a time delay, which is based on the length and width of the wire, the number of devices to which it is connected and the technology used. Therefore, as wires get longer, the delay also increases and it takes a greater amount of time for a signal to propagate from one end of the wire to the other end. Much of the logic within an IC is driven synchronously. In other words, an internal clock controls much of the logic. Typically, during each clock cycle, each functional block performs an operation such that the result is ready prior to the next clock cycle. As technology improves, these delays associated with wire lengths are proportionally larger percentage of this clock cycle. In fact, when an IC is being developed, it is common that the propagation delay of certain wires can exceed the clock cycle. As the development of the IC progresses, these longer wires must be shortened so that the delay associated with each path is less than the clock cycle. Often, this is done by modifying the logic. In extreme cases, the wire, and the delay, cannot be shortened enough. This forces the designer to change significant portions of the IC to comply with the timing requirements. These changes can force schedule delays, which are obviously undesirable.
While the cross bar switch significantly reduces the number of wires, it is not without some drawbacks. To reduce routing congestion and achieve the shortest wire lengths, the cross bar switch is preferably located in the center of the IC. This can be problematic if the chip has other centralized functions that would be best located in the center of the IC. For example, network switching Ics often have centralized functions, such as scheduling logic, and memory, that is preferably located in the center of the chip. Thus, it would be desirable to have the advantages of a cross bar switch, without having to dedicate the center of the IC to that function.
A second shortcoming of the cross bar switch is that while careful placement of the switch can help reduce wire delays, the switch cannot shorten the delays of inherently long routes, such as from one side of the IC to the other.